TSMC submits 0.18-micron production application
Officials from Taiwan Semiconductor Manufacturing Company (TSMC) Shanghai indicated that the company had submitted an application to authorities in Taiwan for producing ICs on 0.18-micron in China, according to a Chinese-language Commercial Times report. The officials were cited as saying that the Shanghai fab will soon meet an economy of scale at 30,000 8-inch wafers in late August and that the foundry would not further expand capacity.
TSMC 0.18-Micron technology is a single poly, six metal layer process with low-k dielectrics. TSMC defines its “true” 0.18-Micron process technology as not only CMOS FET gates with a drawn dimension of 0.18-ms, but also layout and interconnect design rules that are appropriate to the new generation. TSMC’s 0.18-Micron technology boasts the industry’s tightest metal pitches with 0.46-m contacted metal layer 1, 0.56-m contacted metal layers 2 through 5, and 0.90-m on metal layer 6. These pitches provide a higher gate density and more die per wafer, which leads to a lower cost per chip.
Comments are closed.