Samsung develops 50nm DRAM chip for DDR2 Memory Modules
Samsung Electronics has announced that it has developed the industry’s first 50nm DDR2 DRAM chip, which will increase production efficiency from the 60nm level by 55%. The new 1Gbit DRAM incorporates advanced technologies such as three-dimensional (3D) transistor design and multi-layered dielectric technology, which greatly enhance performance and data storage capabilities, according to Samsung. Looks like enthusiasts are going to have to wait a bit for these chips to come out as mass production will start sometime in 2008.
With the 50nm DRAM development, we’re continuing our technology leadership, paving the way for our customers to reap not only greater cost efficiencies but also to make superior products,” said Nam Yong Cho, executive vice president of memory sales and marketing at Samsung’s Semiconductor Business. According to Samsung, key to the production efficiencies in the newly developed 50nm process is the use of a selective epitaxial growth transistor (SEG Tr). The 3D transistor has a broader electron channel that optimizes the speed of each chip’s electrons to reduce power consumption and enable higher performance. Continued miniaturization of the overall memory circuit and an increasingly limited area of coverage within a wafer cell make it much harder to secure and sustain sufficient volumes of electrons. Adding to the 50nm design improvements, the SEG transistor introduces a multi-layered dielectric layer (ZrO2/Al2O3/ZrO2) to resolve weak electrical features. In addition, the new dielectric layer sustains higher volumes of electron to increase storage capacity, ensuring higher reliability in storing data.
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