AMD Testing Extreme Ultra-Violet (EUV) Lithography on Chip
AMD, working together with its research partner, IBM, announced it has produced a working test chip utilizing Extreme Ultra-Violet (EUV) lithography for the critical first layer of metal connections across the entire chip. Previous projects utilizing EUV to produce working chip components were only narrow field, covering just a very small portion of the design. The work of AMD, IBM, and their partners at the UAlbany NanoColleges Albany NanoTech Complex, will be presented by Dr. Bruno La Fontaine of AMD at the premier lithography conference in the industry on Tuesday. The paper will show successful integration of full-field EUV lithography into the fabrication process across an entire 22 mm x 33 mm AMD 45 nm node test chip.
The AMD test chip first went through processing at AMDs Fab 36 in Dresden, Germany, using 193 nm immersion lithography, the most advanced lithography tools in high volume production today. The test chip wafers were then shipped to IBMs Research Facility at the College of Nanoscale Science and Engineering (CNSE) in Albany, New York where AMD, IBM and their partners used an ASML EUV lithography scanner installed in Albany through a partnership with ASML, IBM and CNSE, to pattern the first layer of metal interconnects between the transistors built in Germany. After patterning, etch and metal deposition processes, among others, the EUV device structures underwent electrical testing at AMD, with transistors showing characteristics very consistent with those of test chips built using only 193 nm immersion lithography. These wafers will receive additional metal interconnect layers using standard Fab processing so that large memory arrays can also be tested.
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