Intel Cannonlake Added To LLVM’s Clang – AVX-512

One of our readers just pointed us to a story over at Phoronix that states the future Intel desktop processors will support Clang (C language family frontend for LLVM compiler infrastructure project). We aren’t talking about Kaby Lake, the successor to Skylake referred to by many as the Skylake refresh that is due out 2H 2016, but rather the 10-nm Cannonlake processors that are still on track for a late 2017 debut. It appears that Elena Demikhovksy, Senior Software Engineer at Intel Corporation, made a commit over the weekend that shows Intel Cannonlake CPUs do indeed have AVX-512 support (also called by many AVX3). We highly doubt that you’ll see the AVX-512 instruction set on every single Intel Cannonlake processor as Intel will likely disable it on many mainstream processor models (Core i3 & Core i5) and use it as a selling feature for the higher-end Core i7 models.

Intel Cannonlake avx512

The commit by Ms.Demikhovsky shows that Cannonlake CPUs will have AVX-512 support (abx512ifma and avx512vbmi) along with the SHA Extensions and UMIP. The AVX-512 IFMA and VBMI support has been seen in server CPUs, but never desktop processors.
Intel AVX-512 Technology
Is this a big deal? The AVX-512 instruction set was proposed back in 2013 by Intel and processors supporting the feature are just now coming out.  Applications like Prime95 are memory limited right now, but will be able to take advantage of the extra wider registers and execution units to the tune of about twice the peak Floating Point (FP) throughput. AVX-512 will be beneficial in high-performance computing applications, but there really aren’t many applications out right now for the instruction set since the processors support the instructions are only just now becoming available. Word on the street is that Intel Skylake processors could support the AVX-512 instruction set, but they made the decision to disable the feature. AMD’s Zen is expected to have two FMAC 256-bit units that might be able to join together to process 512-bit AVX floating point instructions. Could it be competition from AMD is finally enough for Intel to enable a feature they’ve been sitting on for some time?
Intel CPUs with AVX-512

  • Xeon Phi Knights Landing: AVX-512 F, CDI, ERI and PFI in 2016
  • Xeon Skylake “Purley”: AVX-512 F, CDI, BW, DQ, and VL in 2017
  • Skylake-E
  • Cannonlake
Print